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ADP32F04 | ADP32F04 series products are designed with ADP32 core, built-in with large capacity processing and rich peripherals. The 48 pin QFN packaged DSP with 4000V ESD capability is a cost-effective product. The company also developed its own MPPT scheme using this chip. ADP32F04 is mainly used in high calculation and control fields with strict submission requirements, such as simple frequency converter, BLDC motor control, fan and water pump control, etc. | High performance static CMOS technology | Up to 120MHz main frequency (cycle 8.33ns) |
Low power consumption design (I/O voltage 3.3v, core voltage 1.8v) | |||
On chip LDO (3.3v single power supply) | |||
JTAG boundary scan support | / | ||
High performance 32-bit CPU | 16 x 16 and 32 x 32 (MAC) operations | ||
16 x 16 dual MAC | |||
Harvard bus architecture | |||
Fast interrupt response and handling | |||
Efficient programming with C/C++and assembly language | |||
Chip memory resource | Up to 128k x 16 flash memory (four 8k x16 sectors and six 16k x 16 sectors) | ||
L0 and L1: two 4k x 16 single access random storage spaces (SARAM) | |||
H0: 8k x 16 single access random storage (SARAM) | |||
M0 and M1: two 1k x 16 single access random storage spaces (SARAM) | |||
Boot ROM boot area | With software boot mode | ||
Standard Arithmetic Table | |||
Clock and system control | Support dynamic phase-locked loop (PLL) frequency division coefficient adjustment | ||
On-chip oscillator | |||
Watchdog timer | |||
Three 32-bit CPU timers | / | ||
Motor control peripheral (PWM generation circuit) | 7roadPWM(PWM1、PWM2、PWM3、PWM4、PWM5、PWM6、PWM12) | ||
3 capture units, 1 quadrature encoding circuit | |||
1 power drive protection interrupt pin (T1CTRIP_PDPINTA) | |||
Serial communication peripheral interface | Serial Peripheral Interface (SPI) | ||
One 2-wire asynchronous serial communication interface (SCI, SCIB), standard UART | |||
12 bit 8-channel analog-to-digital converter (ADC) | Two sample and hold circuits | ||
Single/synchronous conversion | |||
Fast conversion rate: 80ns/12.5MSPS | |||
19 general purpose I/O (GPIO) pins | / | ||
Advanced simulation functions | Analysis and breakpoint functions | ||
Hardware based real-time debugging | |||
ADP32F48Digital Signal Processor | / | ||
development tool | ANSI C/C++Compiler/Assembly Language/Connector | ||
Support Code Composer Studio ™ IDE | |||
Supports DSP/BIOS ™ | |||
JTAG Emulator | |||
Low power consumption mode and power saving mode | IDLE, STANDBY and HALT modes are supported | ||
The independent peripheral clock can be disabled | |||
encapsulation | 48 pin QFN package | ||
Product grade | Industrial grade | ||
ADP32F03x | The ADP32F03X DSP series is the latest product on the core feeding electronic fixed-point DSP platform. The controller based on ADP32Fx has the same 32-bit fixed-point architecture as the existing ADP32FxMCU. It is a very efficient C/C++engine, which not only enables users to develop their control system software in high-level languages, but also to develop mathematical algorithms in C/C++. This device is equally effective in processing DSP arithmetic tasks as it is in processing system control tasks, which are usually handled by microcontroller devices. This efficiency eliminates the need for a second processor in many systems. The 32x32 bit MAC function and its 64 bit processing capability enable the device to effectively handle high digital resolution problems. The fast interrupt response with automatic environment saving of key registers inside the device enables the device to handle many asynchronous events with minimum delay. The device also has an 8-level deep protected pipeline with pipelined memory access. This pipelining operation enables the device to execute instructions at high speed without using expensive high-speed memory. In particular, branch ahead hardware greatly reduces the delay caused by conditional discontinuity. Special storage condition operations further improve performance. | High efficiency 32-bit central processing unit (CPU) (ADP32Fx core) | / |
Main frequency 60MHz (cycle 16.67ns) | / | ||
3.3V single power supply | / | ||
Integrated power on and undervoltage reset source | / | ||
On chip flash memory, SRAM, OTP memory | / | ||
Code security module | / | ||
Serial port peripherals (SCI/SPI/I2C/LIN/eCAN) | / | ||
Enhanced control peripherals | Enhanced Pulse Width Modulator (ePWM) | ||
High resolution PWM (HRPWM) | |||
Enhanced Capture (eCAP) | |||
High Resolution Input Capture (HRCAP) | |||
Enhanced quadrature encoder pulse (eQEP) | |||
Analog to Digital Converter (ADC) | |||
On chip temperature sensor | |||
comparator | |||
High efficiency 32-bit central processing unit (CPU) (ADP32Fx) | 60MHz (16.67ns cycle time) | ||
16 x 16 and 32 x 32 Multiply Accumulate (MAC) operations | |||
16 x 16 dual MAC | |||
Harvard bus architecture | |||
Linked operation | |||
Fast interrupt response and handling | |||
Unified Memory Programming Model | |||
Efficient code (using C/C++and assembly language) | |||
Programmable Control Law Accelerator (CLA) | 32-bit floating point arithmetic accelerator | ||
Code execution independent of the main CPU | |||
Strong ESD protection capability | ESD human body mode (HBM):+2000V/- 2000V | ||
low cost | No power sequencing required | ||
Integrated power on reset and undervoltage reset | |||
low power consumption | |||
No analog support pin | |||
Clock and system control | Two internal zero pin oscillators | ||
On chip oscillator/external clock input | |||
Support dynamic phase-locked loop (PLL) ratio change | |||
Lost clock detection circuit | |||
Up to 45 individually programmable multiplexed GPIOs with input filtering | / | ||
Peripheral interrupt expansion (PIE) module that can support all peripheral interrupts | / | ||
Three 32-bit CPU timers | / | ||
Each ePWM module contains an independent 16 bit timer | / | ||
Chip memory | Flash memory, SRAM, OTP, boot ROM available | ||
128 bit security key/lock | Secure memory blocks | ||
Prevent hardware reverse engineering | |||
Serial port peripherals | One SCI (UART) module | ||
Two SPI modules | |||
An internal integrated circuit (I2C) bus | |||
A Local Interconnect Network (LIN) bus | |||
An enhanced controller area network (eCAN) bus | |||
Advanced Simulation Features | Analysis and breakpoint functions | ||
Packaging Options | 56 pin ultra small square flat no pin (VQFN) package | ||
64 pin thin quad flat (LQFP) package | |||
80 pin thin square flat (LQFP) package | |||
48 pin thin quad flat (LQFP) package | |||
ADP32F1x | A high-performance 32-bit fixed-point digital processor with low power consumption and high performance. Built in a variety of memories and rich peripherals, with a wide range of applications. It can be used in industrial intelligent control, Internet of Things wireless access, variable frequency electric drive, general signal processing and other fields. | High performance CMOS process | Main frequency 150MHz (cycle 6.67ns) |
Low power consumption design (1.8V core, 3.3V I/O voltage) | |||
Integrated 1.8V linear regulated power supply (LDO) | |||
Support JTAG online simulation | / | ||
High performance 32-bit CPU | Single cycle 32-bit x32 bit multiply accumulate (MAC) operation | ||
Two 16 bit x16 bit multiply accumulate (MAC) operations in a single cycle | |||
Harvard bus architecture | |||
Atomic operation | |||
Fast interrupt response and handling | |||
Unified register programming mode | |||
4M linear program/data address | |||
Efficient programming with C/C++and assembly language | |||
Chip memory resource | Flash memory: 128K x 16 bit flash memory (4 8Kx16 bit and 6 16Kx16 bit sectors) | ||
ROM: 128K x 16 bit ROM (Note: Version C, customized) | |||
1K x 16 OTP ROM | |||
L0 and L1: 2 blocks 4Kx16 bits independently addressed SARAM | |||
H0: 1 block 8K x 16 bit SARAM | |||
M0 and M1: 2 1Kx16 bit independent addressing SARAM | |||
Boot ROM (4K X 16 bit) | Support software boot mode | ||
Standard arithmetic table | |||
External storage expansion interface | More than 1M x 16 bit expandable space | ||
Programmable wait state | |||
Programmable read/write timing | |||
3 independent chip selection signals | |||
Clock and system control | Support dynamic phase-locked loop (PLL) frequency division coefficient adjustment | ||
On-chip oscillator | |||
Watchdog timer | |||
Three external interrupt interfaces | / | ||
Peripheral interrupt expansion block (PIE) supporting 45 peripheral interrupts | / | ||
Three 32-bit CPU timers | / | ||
128 bit security key/lock | Protect Flash/ROM/OTP and L0/L1 SARAM | ||
Prevent reverse cracking of firmware | |||
Motor control peripheral (PWM generation circuit) | Event Manager 1 (EM1), Event Manager 2 (EM2) | ||
They include: 2 16 bit timers, 3 numerical comparators, 3 capture units, and 1 orthogonal encoding circuit. | |||
Serial port peripherals | Serial Peripheral Interface (SPI) | ||
Two serial communication interfaces (SCI), compatible with UART standard | |||
Enhanced Controller Area Network (eCAN) controller, integrated on-chip eCAN driver | |||
Multichannel buffered serial port (McBSP) | |||
12 bit 16 channel analog-to-digital converter (ADC) | 2 x 8-channel input multiplexer | ||
Two sample and hold circuits | |||
Single/synchronous conversion | |||
Fast conversion rate: 80ns/12.5MSPS | |||
56 general purpose I/O (GPIO) pins | / | ||
Advanced simulation functions | Analysis and breakpoint functions | ||
Hardware based real-time debugging | |||
development tool | ANSI C/C++Compiler/Assembly Language/Connector | ||
Support Code Composer Studio ™ IDE | |||
Supports DSP/BIOS ™ | |||
JTAG Emulator | |||
Low power consumption mode and power saving mode | IDLE, STANDBY and HALT modes are supported | ||
The independent peripheral clock can be disabled | |||
Strong ESD protection capability | ESD human body mode (HBM):+4000V/- 4000V | ||
ESD machine mode (MM):+400V/- 400V | |||
Latch up trigger current: 400mA | |||
Packaging Options | BGA 179 (with external memory interface) | ||
LQFP176 (with external memory interface) | |||
LQFP128 (no external memory interface) | |||
Product grade | G: Industrial grade | ||
C: Consumption grade | |||
ADP32F4408 | ADP32F4408 series products use high-performance 32-bit fixed-point processor core, built-in large capacity processing and rich peripherals, and a variety of small package designs. It is a cost-effective product. It is suitable for simple frequency converter, BLDC motor control, fan and water pump control and other application fields. | High performance static CMOS technology | Up to 120MHz main frequency (cycle 8.33ns) |
Low power consumption design (I/O voltage 3.3v, core voltage 1.8v) | |||
On chip LDO (3.3v single power supply) | |||
JTAG boundary scan support | |||
High performance 32-bit CPU | 16 x 16 and 32 x 32 (MAC) operations | ||
16 x 16 dual MAC | |||
Harvard bus architecture | |||
Fast interrupt response and handling | |||
Efficient programming with C/C++and assembly language | |||
Chip memory resource | Up to 128k x 16 flash memory (four 8k x16 sectors and six 16k x 16 sectors) | ||
L0 and L1: two 4k x 16 single access random storage spaces (SARAM) | |||
H0: 8k x 16 single access random storage (SARAM) | |||
M0 and M1: two 1k x 16 single access random storage spaces (SARAM) | |||
Boot ROM boot area | With software boot mode | ||
Standard Arithmetic Table | |||
Clock and system control | Support dynamic phase-locked loop (PLL) frequency division coefficient adjustment | ||
On-chip oscillator | |||
Watchdog timer | |||
Three 32-bit CPU timers | |||
Motor control peripheral (PWM generation circuit) | 6路PWM(PWM1~PWM6) | ||
3 capture units and 1 quadrature encoding circuit. | |||
1 power drive protection interrupt pin (T1CTRIP_PDPINTA) | |||
串行通讯外设接口 | One 2-wire asynchronous serial communication interface (SCI), standard UART | ||
12 bit 8-channel analog-to-digital converter (ADC) | 2 x 6 channel input multiplexer | ||
Two sample and hold circuits | |||
Single/synchronous conversion | |||
Fast conversion rate: 80ns/12.5MSPS | |||
8 general purpose I/O (GPIO) pins | |||
Advanced simulation functions | Analysis and breakpoint functions | ||
Hardware based real-time debugging | |||
development tool | ANSI C/C++Compiler/Assembly Language/Connector | ||
Support Code Composer Studio ™ IDE | |||
Supports DSP/BIOS ™ | |||
JTAG Emulator | |||
Low power consumption mode and power saving mode | IDLE, STANDBY and HALT modes are supported | ||
The independent peripheral clock can be disabled | |||
encapsulation | 44 pin LQFP package (pin pitch 0.8mm) | ||
Product grade | Industrial grade | ||
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